From b5ae219dc9a8b841ff63b06292f6c9f719ebf8f5 Mon Sep 17 00:00:00 2001 From: Alexey Kopytov Date: Thu, 8 Sep 2016 17:26:50 +0300 Subject: [PATCH] Bug #82890: RDTimeStampCounter.TestCycle test failure. RDTimeStampCounter.TestCycle unit test expects that the cycle timer counter will overflow. The AArch64 cycle timer implementation uses a 64-bit register, so it is unreasonable to expect overflow, whereas the condition in the unittest expects at least 1 overflow for some reasons. Fixed by changing the unittest to not expect an overflow which was likely the original intent. --- unittest/gunit/mysys_my_rdtsc-t.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/unittest/gunit/mysys_my_rdtsc-t.cc b/unittest/gunit/mysys_my_rdtsc-t.cc index 6d3460e..b287cfd 100644 --- a/unittest/gunit/mysys_my_rdtsc-t.cc +++ b/unittest/gunit/mysys_my_rdtsc-t.cc @@ -117,7 +117,7 @@ TEST_F(RDTimeStampCounter, TestCycle) #if defined(__aarch64__) /* The ARM cycle timer has low resolution */ EXPECT_EQ(LOOP_COUNT, nonzero); - EXPECT_NE(0, backward); + EXPECT_EQ(0, backward); #else /* Expect at most 1 backward, the cycle value can overflow */ EXPECT_TRUE((backward <= 1)) << "The cycle timer is strictly increasing";