From 686d2255249ab6107246d0500bf4a12e1dfc9130 Mon Sep 17 00:00:00 2001
From: Namrata Bhave <Namrata.Bhave@ibm.com>
Date: Thu, 21 Apr 2022 10:38:31 +0530
Subject: [PATCH] Fix incorrect value of CACHELINESIZE on s390x

---
 sql/memory/aligned_atomic.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/sql/memory/aligned_atomic.h b/sql/memory/aligned_atomic.h
index 8ec10f478238..d4851dd97543 100644
--- a/sql/memory/aligned_atomic.h
+++ b/sql/memory/aligned_atomic.h
@@ -35,6 +35,7 @@
 #include <windows.h>
 #elif defined(__linux__)
 #include <unistd.h>
+#include <cstdio>
 #endif
 
 namespace memory {
@@ -79,6 +80,13 @@ static inline size_t _cache_line_size() {
 static inline size_t _cache_line_size() {
   long size = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
   if (size == -1) return 64;
+  if (!size) {
+    FILE* p = fopen("/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size", "r");
+    if (p) {
+      fscanf(p, "%ld", &size);
+      fclose(p);
+    }
+  }
   return static_cast<size_t>(size);
 }