| Bug #100432 | Optimal memory-barrier for performance-schema counter | ||
|---|---|---|---|
| Submitted: | 5 Aug 2020 7:55 | Modified: | 5 Aug 2020 13:15 |
| Reporter: | Krunal Bauskar | Email Updates: | |
| Status: | Verified | Impact on me: | |
| Category: | MySQL Server: Performance Schema | Severity: | S5 (Performance) |
| Version: | 8.0.21 | OS: | Any |
| Assigned to: | CPU Architecture: | ARM | |
| Tags: | arm, memory barrier, performance | ||
[5 Aug 2020 7:55]
Krunal Bauskar
pfs memory barrier patch
Attachment: perf#pfs-memory-barrier.patch (text/x-patch), 16.32 KiB.
[5 Aug 2020 13:15]
MySQL Verification Team
Hi Mr. Bauskar, Thank you for your performance improvement report, for the ARM family of CPUs. However, thank you even more for your patch, which looks quite promising to me. Verified as reported.
Description: - performance-schema is filled with counters to track different aspects. Most of these counters use default memory-order that is sequential-consistent. - Given these are tracking counters and not meant to synchronize threads, memory order of these counters could be switched over to relaxed. How to repeat: * I will submit the patch that could be used to see the difference. Steps to reproduce: ------------------- Enable the wait events: UPDATE performance_schema.setup_instruments SET ENABLED = 'YES', TIMED = 'YES' WHERE NAME LIKE 'wait/%'; UPDATE performance_schema.setup_consumers SET ENABLED = 'YES' WHERE NAME LIKE 'events_waits%'; Run any workload (I tried sysbench update-non-index workload with 1024 threads (zipfian and uniform)) ________________________________________________________________________________ ARM --- zipfian ======== perf % tps baseline 18.02% [.] insert_events_waits_history_long 7103 patched 15.56% [.] insert_events_waits_history_long 7630 (+7%) uniform ======== perf % tps baseline 2.97% [.] insert_events_waits_history_long 7403 patched 2.34% [.] insert_events_waits_history_long 8300 (+12%) x86 --- zipfian ======== perf % tps baseline 5.36% [.] insert_events_waits_history_long 39534 patched 4.81% [.] insert_events_waits_history_long 40001 (+1.1%) uniform ======== perf % tps baseline 7.22% [.] insert_events_waits_history_long 48362 patched 6.11% [.] insert_events_waits_history_long 49618 (+2.6%)